In the field of digital logic, extensive use is made of well known and highly developed complementary metal-oxide semiconductor (CMOS) technology. As CMOS has begun to approach maturity as a technology, there is an interest in alternatives that may lead to higher performance in terms of speed, power dissipation computational density, interconnect bandwidth, and the like. An alternative to CMOS technology comprises superconductor based single flux quantum circuitry, utilizing superconducting Josephson junctions, with typical signal power of around 4 nanowatts (nW), at a typical data rate of 20 gigabits per second (Gb/s) or greater, and operating temperatures of around 4 kelvins.
A non-destructive readout (NDRO) circuit is a circuit that can retrieve a stored information state (e.g., one or multiple bits) for transmission to other circuitry for processing or output without erasing, destroying, changing, or otherwise corrupting the stored information state. For the purposes of this application, the term should not be interpreted to include circuits that destructively retrieve a stored information state but then thereafter perform a restorative write-back.
Latches and flip-flops are circuits that can be used to store state information and to change state by signals applied to one or more control inputs. In modern computing and communications electronics, these are basic storage elements in memories and sequential logic. A latch is asynchronous, with its output changing as soon as its data input does (or at least after a small propagation delay), provided the latch is enabled via an enable input. A flip-flop is synchronous and edge-triggered and only changes state when a clocking control signal goes from high to low or low to high. Thus, a conventional D flip-flop, e.g., one implemented in CMOS, has two binary inputs, a data input D and a clock input, and at least one output, Q. The D flip-flop captures the value of the D input at a definite portion of an input clock cycle, e.g., a rising edge or a falling edge, known as the capture time. That captured value becomes the Q output. The output Q does not change except at the capture time (or some small propagation delay thereafter). In practical implementations it is required that a data input D be stable for some setup time prior to the capture time and for some hold time after the capture time for the input to be reliably captured and propagated to the output. A conventional D latch, with an enable input rather than a clock input, behaves similarly, except that the output can change according to the data input so long as an enable input remains asserted.
In the context of superconducting reciprocal quantum logic (RQL) circuits, phase-mode logic (PML) allows digital values to be encoded as superconducting phases of one or more Josephson junctions. For example, a logical “1” may be encoded as a high phase and a logical “0” may be encoded as a low phase. For example, the phases may be encoded as being zero radians (meaning, e.g., logical “0”) or 2π radians (meaning, e.g., logical “1”). These values persist across RQL AC clock cycles in PML because there is no requirement for a reciprocal pulse to reset the Josephson junctions phase. In contrast to PML, in wave-pipelined logic (WPL), a logical “1” is encoded as a positive single flux quantum (SFQ) pulse followed by a reciprocal negative pulse, whereas a logical “0” is encoded as the absence of either such pulse.